Patents

  • DMA Engines Configured to Perform First Portion Data Transfer Commands with a First DMA Engine and Second Portion Data Transfer Commands with Second DMA Engine
    Joseph L. Greathouse, Sean Keely, Alan D. Smith, Anthony Asaro, Ling-Ling Wang, Milind N. Nemlekar, Hari Thangirala, Felix Kuehling
    Patent: Google Patents | PDF
    Patent Number: US 11,995,351
    Granted: May 28, 2024
  • Hardware Device for Enforcing Atomicity for Memory Operations
    Vydhyanathan Kalyanasundharam, Joseph L. Greathouse, Shyam Sekhar
    Patent: Google Patents | PDF
    Patent Number: US 11,972,261
    Granted: April 30, 2024
  • Compiler-initiated Tile Replacement to Enable Hardware Acceleration Resources
    Gregory P. Rodgers, Joseph L. Greathouse
    Patent: Google Patents | PDF
    Patent Number: US 11,853,734 (Continuation of US 11,347,486)
    Granted: December 26, 2023
  • Dynamic Repartition of Memory Physical Address Mapping
    Joseph L. Greathouse, Alan D. Smith, Francisco L. Duran, Felix Kuehling, Anthony Asaro
    Patent: Google Patents | PDF
    Patent Number: US 11,687,251
    Granted: June 27, 2023
  • Allreduce Enhanced Direct Memory Access Functionality
    Abhinav Vishnu, Joseph L. Greathouse
    Patent: Google Patents | PDF
    Patent Number: US 11,669,473
    Granted: June 6, 2023
  • Family of Lossy Sparse Load SIMD Instrutions
    Sanchari Sen, Derrick Allen Augren, Joseph L. Greathouse
    Patent: Google Patents | PDF
    Patent Number: US 11,663,001
    Granted: May 30, 2023
  • Dynamic Modification of Coherent Atomic Memory Operations
    Joseph L. Greathouse, Steven Tony Tye, Mark Fowler, Milind N. Nemlekar
    Patent: Google Patents | PDF
    Patent Number: US 11,604,737
    Granted: March 14, 2023
  • Per-instruction Energy Debugging Using Instruction Sampling Hardware
    Shijia Wei, Joseph L. Greathouse, John Kalamatianos
    Patent: Google Patents | PDF
    Patent Number: US 11,556,162
    Granted: January 17, 2023
  • Compiler-initiated Tile Replacement to Enable Hardware Acceleration Resources
    Gregory P. Rodgers, Joseph L. Greathouse
    Patent: Google Patents | PDF
    Patent Number: US 11,347,486
    Granted: May 31, 2022
  • Enforcing Central Processing Unit Quality of Service Guarantees When Servicing Accelerator Requests
    Arkaprava Basu, Joseph L. Greathouse
    Patent: Google Patents | PDF
    Patent Number: US 11,275,613
    Granted: March 15, 2022
  • Runtime Localized Cooling of High-Performance Processors
    Karthik Rao, Wei Huang, Xudong An, Manish Arora, Joseph L. Greathouse
    Patent: Google Patents | PDF
    Patent Number: US 11,137,809
    Granted: October 5, 2021
  • Optimized and Scalable Sparse Triangular Linear Systems on Networks of Accelerators
    Khaled Hamidouche, Michael W. LeBeane, Nicholas P. Malaya, Joseph L. Greathouse
    Patent: Google Patents | PDF
    Patent Number: US 10,936,697
    Granted: March 2, 2021
  • Distributed Multi-Input Multi-Output Control Theoretic Method to Manage Heterogeneous Systems
    Raghavendra Pradyumna Pothukuchi, Joseph L. Greathouse, Leonardo de Paula Rosa Piga
    Patent: Google Patents | PDF
    Patent Number: US 10,928,789
    Granted: February 23, 2021
  • Method and Apparatus for Temperature-Gradient Aware Data-Placement for 3D Stacked DRAMs
    Jagadish B. Kotra, Karthik Rao, Joseph L. Greathouse
    Patent: Google Patents | PDF
    Patent Number: US 10,725,670
    Granted: July 28, 2020
  • Heterogeneous Graphics Processing Unit for Scheduling Thread Groups for Execution on Variable Width SIMD Units
    Joseph L. Greathouse, Mitesh R. Meswani, Sooraj Puthoor, Dmitri Yudanov, James M. O'Connor
    Patent: Google Patents | PDF
    Patent Number: US 10,713,059
    Granted: July 14, 2020
  • High-Performance Sparse Triangular Solve on Graphics Processing Units
    Joseph L. Greathouse
    Patent: Google Patents | PDF
    Patent Number: US 10,691,772
    Granted: June 23, 2020
  • Dynamically Adapting Mechanism for Translation Lookaside Buffer Shootdowns
    Arkaprava Basu, Joseph L. Greathouse
    Patent: Google Patents | PDF
    Patent Number: US 10,552,339
    Granted: February 4, 2020
  • Detecting Buffer Overflows in General-Purpose GPU Applications
    Joseph L. Greathouse, Christopher D. Erb, Michael G. Collins
    Patent: Google Patents | PDF
    Patent Number: US 10,067,710
    Granted: September 4, 2018
  • Predicting a Context Portion to Move Between a Context Buffer and Registers Based on Context Portions Previously Used by at least One Other Thread
    Dmitri Yudanov, Sergey Blagodurov, Arkaprava Basu, Sooraj Puthoor, Joseph L. Greathouse
    Patent: Google Patents | PDF
    Patent Number: US 10,019,283
    Granted: July 10, 2018
  • Hardware Accuracy Counters for Application Precision and Quality Feedback
    Leonardo de Paula Rosa Piga, Abhinandan Majumdar, Indrani Paul, Wei Huang, Manish Arora, Joseph L. Greathouse
    Patent: Google Patents | PDF
    Patent Number: US 9,990,203
    Granted: June 5, 2018
  • Efficient Sparse Matrix-Vector Multiplication on Parallel Processors
    Mayank Daga, Joseph L. Greathouse
    Patent: Google Patents | PDF
    Patent Number: US 9,697,176
    Granted: July 4, 2017
  • Randomly Branching Using Hardware Watchpoints
    Joseph L. Greathouse, David S. Christie
    Patent: Google Patents | PDF
    Patent Number: US 9,483,379
    Granted: November 1, 2016
  • Randomly Branching Using Performance Counters
    Joseph L. Greathouse, David S. Christie
    Patent: Google Patents | PDF
    Patent Number: US 9,448,909
    Granted: September 20, 2016
  • User-level Hardware Branch Records
    Joseph L. Greathouse, Anton Chernoff
    Patent: Google Patents | PDF
    Patent Number: US 9,372,733
    Granted: June 21, 2016

Invited Talks

  • Accelerating Dynamic Software Analyses
    Given at Microsoft Research on February 20, 2012
    Video available here
    Presentation: PPTX | PPT | PDF
  • On-Demand Dynamic Software Analysis
    Given for the AMD Tech Topics Series on December 12, 2011
    Presentation: PPTX | PPT | PDF
  • Hardware Support for On-Demand Software Analysis
    Given for the 2011 CSE Graduate Student Honors Competition on December 8, 2011
    Video available here
    Presentation: PPTX | PPT | PDF
  • Accelerating Dynamic Software Analyses
    Given at Microsoft Research, Silicon Valley, on December 2, 2011
    Presentation: PPTX | PPT | PDF
  • Accelerating Dynamic Software Analyses
    Given at VMware on December 1, 2011
    Presentation: PPTX | PPT | PDF
  • On-Demand Dynamic Software Analysis
    Given at Intel Labs, Santa Clara on November 29, 2011
    Presentation: PPTX | PPT | PDF
  • Sampling Dynamic Dataflow Analyses
    Given at the University of British Columbia Computer Science Department on June 10, 2011
    Presentation: PPTX | PPT | PDF

Videos

Posters

  • Scalable Security Vulnerability Analysis via Sampling
    Presented at the 2011 GSRC Annual Symposium, November 16, 2011
    Poster: PDF
  • Testudo: Heavyweight Security Analysis via Statistical Sampling
    Presented at the 2008 University of Michigan Engineering Graduate Symposium, November 2008
    Poster: PDF

Unpublished Works

The following are papers and presentations that I wrote over the course of my graduate studies.
  • Summary Presentation of "Cortical computing with Memristive Nanodevices"
    I presented a summary of this paper about the power of memristors from SciDAC Review at the Adaptive Hardware Reading Group in July 2009
    Presentation: PPTX | PPT | PDF
  • Processors with On-Die Cryptography Accelerators
    This was my final project in EECS 575 during the Winter 2007 semester. It is a survey of cryptography accelerators in the Intel IXP2850, Sun UltraSPARC T1 & T2, and IBM z9.
    Paper: PDF
  • AGEIA PhysX Physics Processing Unit Case Study
    This was a case study presentation done for EECS 573 during the Winter 2007 semester. It looks at the now-defunct Ageia PhysX hardware design. I based this off delving through all of the patents available at that time and from Nicholas Blachford's excellent article.
    Presentation: PPT | PDF
  • A Runtime Metric of Design Confidence
    Ken Zick and I did this research for our EECS 578 final project in the Fall 2006 semester. It is a mechanism to find, at runtime, the best configuration of modules if you are performing N-Version design with the capability to do runtime reconfiguration.
    Paper: PDF
    Presentation: PPT | PDF