Updated April 11, 2018

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Work Experience
  • Advanced Micro Devices, Inc. – Senior Member of Technical Staff
    August 2012 - Present
    I am a performance architect, optimizing software, hardware, and firmware for GPU compute solutions
    Previously researched topics in performance and power monitoring and management in AMD Research.
    Created a new simulator for AMD’s exascale program based on hardware performance monitoring.
    Designed new GPGPU algorithms that accelerated scientific applications and GPGPU correctness tools.
  • University of Michigan – Graduate Student Research Assistant
    May 2007 - August 2012
    Identified methods of distributing software analyses across many users to reduce slowdowns.
    Managed graduate and undergraduate students through development of prototype systems.
  • University of Michigan – Graduate Student Instructor
    January 2012 - April 2012
    Led discussions and evaluated projects for graduate level parallel computer architecture course.
  • Kelly Services / Intel Corp. – Research Contractor
    May 2010 - October 2010
    Researched approaches for improving speed and accuracy of Intel Inspector XE data race detector.
    Utilized unique features of Intel processors to yield orders-of-magnitude performance gains.
  • International Business Machines Corp. – Speed Team Intern
    May 2008 - August 2008
    Designed and constructed an InfiniBand compliance verification suite that caught numerous bugs.
    Instituted suite use into the IBM PowerVM I/O firmware development process.
  • University of Illinois – Teaching Assistant
    January 2005 - August 2006
    Taught discussion sections and graded for undergraduate computer architecture and digital logic courses.
  • University of Michigan, Ann Arbor
    Ph.D., Computer Science and Engineering
    May 2012
    Advisor: Prof. Todd Austin
    Dissertation Topic: Hardware Mechanisms for Distributed Dynamic Software Analysis
  • University of Michigan, Ann Arbor
    M.S.E. Computer Science and Engineering
    May 2008
    Concentration: Hardware Systems
    GPA: 7.73/9.0 (3.79/4.0)
  • University of Illinois at Urbana-Champaign
    B.S. Computer Engineering with Honors
    May 2006
    Minor: International Engineering – Japanese
    GPA: 3.71/4.0
Selected Publications
  • Vignesh Adhinarayanan, Indrani Paul, Joseph L. Greathouse, Wei Huang, Ashutosh Pattnaik, Wu-chun Feng, "Measuring and Modeling On-Chip Interconnect Power on Real Hardware," in the Proceedings of the 2016 IEEE International Symposium on Workload Characterization (IISWC), Sept. 2016. – Awarded Best Pape
  • Gene Wu, Joseph L. Greathouse, Alexander Lyashevsky, Nuwan Jayasena, Derek Chiou, "GPGPU Performance and Power Estimation Using Machine Learning," in the Proceedings of the 21st IEEE Symposium on High Performance Computer Architecture (HPCA), Feb. 2015
  • Joseph L Greathouse, Mayank Daga, "Efficient Sparse Matrix-Vector Multiplication on GPUs using the CSR Storage Format," in the Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis (SC), Nov. 2014
  • Bo Su, Joseph L. Greathouse, Junli Gu, Michael Boyer, Li Shen, Zhiying Wang, "Implementing a Leading Loads Performance Predictor on Commodity Processors," in the Proceedings of the 2014 USENIX Annual Technical Conference (USENIX ATC), June, 2014.
  • Joseph L. Greathouse, Zhiqiang Ma, Matthew I. Frank, Ramesh Peri, Todd Austin, "Demand-Driven Software Race Detection using Hardware Performance Counters," in the Proceedings of the 38th Annual International Symposium on Computer Architecture (ISCA 2011), June 2011
Research Projects
  • AMD Research Instruction Based Sampling Toolkit
    Released a toolkit to allow easy user access to low-level AMD performance monitoring hardware, IBS.
    Available at https://github.com/jlgreathouse/AMD_IBS_Toolkit
  • clARMOR – An OpenCL Kernel Buffer Overflow Detector
    Transferred research on OpenCL kernel buffer overflow detection to productization
    Available at https://github.com/ROCm-Developer-Tools/clARMOR
  • clSPARSE - GPU Accelerated Sparse Linear Algebr
    Transferred research on sparse linear algebra algorithms to open source vendor-optimized library
    Available at https://github.com/clMathLibraries/clSPARSE
  • High-Level Performance and Power Simulator
    Created CPU and GPU power and performance models based on scaling real HW measurements.
    Demonstrated highly accureate estimations (in line with cycle-level simulators) with miniscule slowdown
  • Demand-Driven Dynamic Data Race Detection
    Utilized hardware performance counters to dynamically observe shared memory accesses.
    Integrated this into Intel Inspector XE race detector, yielding large speedups when little sharing occurs.
  • Programming Languages
    C, C++, OpenCL, x86 assembly, AMD GCN assembly, Python
  • Software Systems
    Linux kernel, Intel Pin, multiple AMD-internal simulation, firmware, and analysis tools
Relevant Coursework
  • Computer Architecture
  • Parallel Computer Architecture
  • Microarchitecture
  • Enterprise Systems
  • Advanced Operating Systems
  • Advanced Compilers
  • Electronic Circuits
  • IC Device Theory and Fabrication
Awards and Honors
  • Eta Kappa Nu Electrical and Computer Engineering Honor Society
  • Tau Beta Pi Engineering Honor Society
  • 2016 International Symposium on Workload Characterization Best Paper Award
  • 2011 International Symposium on Code Generation and Optimization Best Student Presentation Award
  • Illinois Chancellor's Scholar
  • Illinois Engineering James Scholar
  • University of Michigan EECS Departmental Fellowship 2006-2007
Associations and Activities
  • Association for Computing Machinery, Senior Member
  • Institute of Electrical and Electronics Engineers
  • Program committee member for ISPASS (2012), HPPAC (2015–2018)
  • External reviewer for ASPLOS (2012, 2013), CODES (2011), DATE (2008–2012), FMCAD (2010), HPCA (2009, 2010, 2012–2014), ISCA (2009, 2010, 2012), MICRO (2008, 2009, 2011, 2012–2014), PACT (2012), and SRCS (2013)
  • Judge at SRC TechCon (2015)