DVFS Space Exploration in Power Constrained Processing-in-Memory Systems


Published in the Proceedings of the 30th International Conference on Architecture of Computing Systems (ARCS 2017), April, 2017 (acceptance rate: 19/42 ≈ 45%


Marko Ščrbak, Joseph L. Greathouse, Nuwan Jayasena, Krishna Kavi


In order to deliver high performance under stringent power constraints, future systems may include die-stacked memories with processing-in-memory (PIM) cores. Because of their proximity to the memory, PIMs are expected to target applications which require high bandwidth, implying that PIMs do not need the same computational capabilities as traditional host processor and can therefore be implemented using slower, low-leakage transistors to increase energy efficiency. Such systems must carefully balance design-time choices, such as the circuits used to build the devices, and run-time choices, such as DVFS states and the preferred hardware platform on which to run the applications. This paper explores these parameters in a GPGPU PIM system with a large compute-optimized host and a collection of bandwidth-optimized PIMs. We develop high-level performance and power models and use them to find optimal DVFS and kernel placement decisions for a series of GPGPU applications targeting maximum energy efficiency. We find, for instance, that the energy efficiency of PIM systems is greatly affected by DVFS; simply selecting the optimum hardware (host/PIM) results in 7x higher ED2 than migrating work in conjunction with DVFS.


The final publication is available at Springer via http://dx.doi.org/10.1007/978-3-319-54999-6_17


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